Floating gate MOS transistors making use of Fowler-Nordheim tunneling of electrons are useful in a plurality of applications, particularly programmable memory devices such as EPROMs and EPALs. In typical applications, a large number of floating gate MOS transistors are formed onto a substrate in an integrated circuit thereby forming a high-density memory array. The reliability of such an array of programmable memory devices is generally dependent upon the failure of single, isolated bits in the array.
FIG. 1a shows a typical floating gate transistor 10 having source 12 and drain 14, generally formed of N+ doped regions; floating gate 15, generally formed of a group I polysilicon; control gate 16, generally formed of a group II polysilicon; and dielectric silicon oxide (SiO.sub.2) layer 18.
To be useful, the floating gate transistor 10 is charged and discharged in accordance with its use in the particular application.
In order to charge or program a particular floating gate transistor, a programming voltage V.sub.pp, on the order of 5-20 volts, is applied to the control gate electrode 16, while source 12 and drain 14 are held at ground or allowed to float. Upon applying V.sub.pp to the control gate 16, capacitive coupling between the control gate 16 and the floating gate 15 causes the floating gate 15 to acquire electrons from the drain region 14 through the process of Fowler-Nordheim tunneling. When V.sub.pp is removed, the floating gate 15 assumes a negative voltage due to the presence of the trapped electrons on the floating gate 15.
Discharge of electrons from the floating gate is generally accomplished by grounding the control gate 16, and applying the programming voltage V.sub.pp to the drain 14 while allowing the source 12 to float.
In a typical high-density memory array, a certain percentage of floating gate transistors used in the memory cells will exhibit atypical charge/discharge characteristics. These atypical cells comprise "weak" bits in the memory array. An atypical cell is defined as a cell which, after a number of charge/discharge cycles, fails to charge/discharge properly because of a breakdown of the tunnel dielectric caused by excessive electron tunneling. A typical bit performs charge/discharge functions for the period of time expected by the hardware designer, taking into account the particular materials used and the parameters of the floating gate transistor, such as oxide thickness, length, width, and implantation concentration. In general, the endurance of a typical bit in the array is generally orders of magnitude better than those of the weak bit.
The endurance of an oxide layer depends on the quality of the SiO.sub.2 tunneling dielectric, which is a function of the amount of charge which can be made to pass through the dielectric before breakdown of the floating gate occurs. This is normally referred to as "fluence" or Q.sub.BD. When the term "endurance" is used with respect to a memory array, the term refers to the length of time the particular array will function before a failure in a "weak" bit occurs.
A failure of any particular weak bit in a memory array thus reduces the endurance of the array. It is then desirable to reduce the failure rate of weak bits within an array to improve the overall endurance of the memory chip.
It is thus an object of the invention to improve the reliability of a floating gate transistor.
It is a further object of the invention to improve the endurance of a memory array using floating gate transistors.
It is another object of the present invention to provide the above objects in an electrically erasable programmable memory cell.
It is a further object of the invention to improve the endurance of a floating gate transistor by controlling the tunneling current through the dielectric layer of the transistor during discharge of the floating gate.
It is a further object of the invention to provide the above objects in a floating gate transistor configuration which optimizes the electric field potential at the tunnel region of the dielectric insulating layer during discharge of the floating gate.